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الكلية كلية التربية للعلوم الصرفة
القسم قسم الفيزياء
المرحلة 3
أستاذ المادة حمد رحمن جبر البركاوي
27/05/2018 10:18:00
8.1 Introduction: A counter is an electronic device which is able to generate an orderly sequence of binary numbers. The addresses which command digital circuits as decoder, multiplexer, demultiplexer etc. are most of the time generated by counters. There two main basic types of counters: asynchronous counter and synchronous counter. Counters are designed using flip-flops, usually J-K flip-flops. Asynchronous counters functions in such a way that the clock signal does not affect all the flip-flops at the same instant; in fact, the clock signal triggers the first flipflop which in his turn trigger the second flip-flop using its output signal. The second flip-flop in his turn will trigger the third one, and so on, till the last flip-flop. It is just like the triggering signal was being propagated from the first flip-flop to the last. For this reason, asynchronous counters are also called propagation counters. The flip-flops of a synchronous counter are all triggered by the same clock signal at the same instant. In fact, all the flip-flops function in synchronism with the clock signal. The outputs of all the flip-flops change their status at the same instant. 8.2 Asynchronous counters: Let us consider the following binary count sequence. The numbers are coded in four bits. Q0 is the LSB and Q3 is the MSB. It can be noticed that each bit in this four-bit sequence toggles when the bit before it (the bit having a lesser significance or place weight), toggles from 1 to 0. Small arrows are used to indicate those places in the above count sequence. So, to design an asynchronous counter which is able to generate the above sequence of numbers, we need to determine how to connect the clock inputs of each of the four J-K flip-flops (each flip-flop generating one bit) in such a way that each bit will toggle only when the bit just before it is transitioning from 1 to 0. The easier way of doing that is to use flip-flops with negative edge triggering. The clock input of each flip-flop will simply be connected to the non-complemented output Q of the flip-flop situated just before it (Flip-flop having one lesser place weight). In this condition, each flip-flop will toggle any time the output of the flip-flop one place lesser weighted than it is transitioning from 1 to 0 (negative edge).
المادة المعروضة اعلاه هي مدخل الى المحاضرة المرفوعة بواسطة استاذ(ة) المادة . وقد تبدو لك غير متكاملة . حيث يضع استاذ المادة في بعض الاحيان فقط الجزء الاول من المحاضرة من اجل الاطلاع على ما ستقوم بتحميله لاحقا . في نظام التعليم الالكتروني نوفر هذه الخدمة لكي نبقيك على اطلاع حول محتوى الملف الذي ستقوم بتحميله .
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